The European Telecommunications Standard number ETS 300 800, known also as the DVB-RC (Digital Video Broadcasting-Return Channel) standard and compliant with the DAVIC (Digital Audio-Visual Council) 1.4 standard, lays down the general framework for implementing an uplink transmission channel as a part of bidirectional communication over a cable television network. An apparatus known as the cable modem, which is a basically known part of the terminal arrangement located at e.g. a private home, is allowed to emit transmissions in the uplink direction according to a certain schedule. A centrally located device known as the head-end composes the uplink transmission schedule and communicates the allocated uplink transmission time intervals to the cable modems. The messages that comprise these allocations are known as MAC or Media Access Control messages, and they are complemented by the information of MAC Flags included in the downlink transmission.
FIG. 1 illustrates some known aspects of the timing of the uplink transmissions. The downlink transmission which the cable modems are listening to contains a synchronization signal which comprises time indicators or markers 101 that occur regularly with one or three millisecond intervals. The downlink transmission may come either in an out-of-band (OOB) or in-band (IB) form, which makes a small difference to the implementation of the markers 101. An OOB downlink transmission consists of a continuous stream of downlink data structures known as SL-ESFs (Signalling Link Extended Superframes). Each SL-ESF contains 4632 bits, of which bits number 0, 1544 and 3088 are available as marker bits. The use of these bits differs slightly depending on the data rate of the OOB downlink transmission, but basically the moment of occurrence of a certain downlink bit constitutes the marker. An IB downlink transmission consists of so-called MPEG2-TS packets where a certain upstream slot marker pointer indicates the number of symbol clock cycles between the first symbol of the next synchronization byte and the next 3 ms marker.
Several upstream slot rates are available depending on the upstream data rate to be utilized. The upstream data rate may be 256 kbit/s, 1.544 Mbit/s, 3.088 Mbit/s or 6.176 Mbit/s, corresponding to slot rates of 500, 3000, 6000 or 12 000 upstream slots/s respectively. If we consider the markers to occur at 1 ms intervals, each time interval between two successive markers 101 may comprise half, three, six or twelve allocatable uplink transmission slots. In FIG. 1 the division of one such time interval into six uplink slots S0 to S5 is shown as an example. The upstream slots are numbered according to a certain cyclic numbering scheme which is derived from the downstream frame numbers which are included in the downstream frames. More specifically, the downlink frames comprise a set of so-called M-bits M10–M1 which constitute a register the value of which is incremented by one every 3 ms. The maximum value for the register is calculable from a certain MAC Default Configuration element and the upstream data rate. After the maximum value the register returns to zero. The upstream slot numbers that are valid during a certain 3 ms period are calculated from the register value received during the immediately preceding 3 ms period by multiplying the register value with integer multipliers which are associated with the upstream data rate.
Setting up an uplink connection between a cable modem and the head-end requires some exchange of MAC messages. For the purposes of the invention it is important that when a cable modem responds to the head-end with a certain MAC Sign-On Response message, the head-end calculates certain time offset values which the cable modem should use to correct its uplink transmission timing. In a single-cast MAC Ranging and Power Calibration message to the cable modem the head-end transmits two indicator values known as the Absolute_time_offset and the Time_offset. The range of both offset indicators is ±3 milliseconds with a step size of 100 nanoseconds. Several rounds of calibrating may be needed to find the correct values for the Absolute_time_offset and the Time_offset indicators. Some further exchange of messages completes the sign-on and calibration phase.
When the head-end wants to assign an uplink transmission slot to a certain cable modem, it transmits a certain MAC Connect message where it uses a specific indication scheme to announce to the cable modem the first upstream slot number in which it may begin transmitting, the number of successive assigned slots following the first slot, the cyclic or listed occurrence of following similar slot allocations and the last slot number which the cable modem may use for uplink transmissions. Because the uplink slot numbers are defined in relation to downlink frame numbers, and because the uplink slot positions are synchronized to the markers given within the downlink frames, the cable modem has thereafter all the information it needs to trigger its uplink transmission(s) at exactly given moment(s).
It follows from the known relations between the downlink frame numbers, the location of the markers within the downlink frames and the downlink-uplink synchronization that the assignment of a certain uplink slot determines a certain marker to be used as a reference point. This marker has been designated in FIG. 1 as the zero point 102 in the time base laid down by the markers. The defined maximum ranges of the Absolute_time_offset and Time_offset indicators mean that the actual transmission moment or the allocated uplink slot may be located anywhere within the 12 millisecond interval which lies symmetrically around the reference point 102. It is on the responsibility of the cable modem to decode the allocation of its uplink transmission slot and to trigger the uplink transmission so that it takes place within the limits of the allocated slot.
In practice the range of available offsets may be shorter on the negative offset side (to the left from the reference point 102 in FIG. 1) than 6 milliseconds, because the MAC message/MAC Flags that contains the allocation may come less than 6 milliseconds before the time indicator that is used as the reference point. However, in order to fulfil the standard's requirements the cable modem must be able to time its uplink transmission to any point of time within said 12 ms interval, with offset timing steps of 100 nanoseconds, as defined by the head-end. The required accuracy in triggering the uplink transmission is ±0.625 symbol durations with selected transmission rate.
A microprocessor controls all operations of the cable modem, so in principle it would be possible to instruct the microprocessor to generate a triggering signal to the uplink transmitter in the cable modem so that the uplink transmission would take place exactly at a given moment. However, it is difficult to realize any external triggering with a microprocessor to the required accuracy.
A known hardware-based solution is to have in the cable modem a slot counter that is synchronized to the actual occurrence of the markers seen by the cable modem. In other words the slot counter does not take into account the offset values (the Absolute_time_offset and Time_offset indicators). Additionally a known cable modem contains a number of offset counters. Each offset counter ticks at steps of 100 ns throughout the whole 12 ms interval described above if required. Each offset counter is initialized to give a transmission triggering signal at a time instant that differs from the nominal position of an allocated slot by a time which corresponds to the given Absolute_time_offset and Time_offset values. Since the cable modem must be ready to transmit in each and every uplink transmission slot, and since the maximum number of uplink transmission slots is 12 per millisecond (when the uplink data rate is 6.176 Mbit/s), a total of 12×12=144 offset counters is required.
FIGS. 2a and 2b illustrate the principles of the above-described conventional hardware-based solution. Each offset counter in the offset counter block 201 is reset with an initialization instruction that makes the counter to expire after the combined length of time given by the Absolute_time_offset and Time_offset indicators. The slot counter 203 counts all the time and is synchronized to the markers, of which there is specificallyt shown a marker 202 that marks the beginning of the 12 ms interval referred to above. At the occurrence of each allocated slot, as given by the slot counter 203, an offset counter is started: when that offset counter expires, it gives an expiration signal which acts as the triggering instruction to the uplink transmitter 204.
Not only is the offset counter block 201 physically large in terms of required circuit area within an integrated circuit implementation, but also the accuracy requirements of the clock pulse that is used to advance the counters become quite stringent.